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Glossary - CPU

CSP (Chip-scale packaging) New smaller "packages" for flash devices, such as FBGA and uBGA.

FBGA (Fine-pitch Ball Grid Array) FBGA is a chip-scale package option for AMD flash devices.

Frontside Bus - (FSB). The primary bus interface that connects a microprocessor to other system devices via the Northbridge system chipset. Typically, it allows the processor to communicate with main memory (RAM), the system chipset, PCI devices, the AGP card, and other peripheral buses. It also connects to the Level 2 cache unless the processor has a backside bus.

JEDEC - (Joint Electronic Device Engineering Council). An international body that sets integrated circuit standards.

KGD (Known Good Die) KGD is a process where customers can get fully tested, bare-die flash devices. No additional packaging, like a TSOP, is provided.

kHz Abbreviation for kilohertz, a unit of frequency equal to 1000 cycles per second.

L1 Cache A small amount of SRAM memory used as a cache that is integrated or packaged within the same module as the processor. It is clocked at the same speed of the processor. L1 cache is used to temporarily store instructions and data, making sure the processor has a steady supply of data to process while the memory catches up delivering new data.

L2 Cache Typically consists of SRAM chips near the processor, although the latest Athlon?processors have on-chip L2 caches. This is cache used to temporarily store instructions and data to ensure the processor has a steady supply of data to process until main memory catches up. Also known as the secondary cache, this is the second-fastest memory available to a microprocessor (second only to the Level 1 cache).

MCP (Multi-chip package) A combination of semiconductor devices in one package, usually SRAM and Flash.

MHz Abbreviation for megahertz, a unit of frequency equal to 1,000,000 cycles per second.

Smart MP technology Smart MP technology features dual point-to-point, high-speed 266MHz system buses, an optimized "MOESI" cache coherency protocol, which manages data and memory traffic, as well as innovative "snoop" buses, which offer high-speed communication between the CPUs in a multiprocessing system. Smart MP technology is designed to optimize the execution of multi-threaded, mission-critical applications empowering your enterprise to achieve new levels of productivity.

Snoop bus AMD's innovative "Snoop" bus is a high-speed, inter-processor communications bus used in the AMD Athlon MP processor-based platform. It facilitates the transfer between the CPU cache to reduce memory bandwidth requirements for shared data.

TeamDDR (www.teamddr.com). TeamDDR is a collaborative effort among DRAM manufacturers and suppliers, system developers, processor suppliers, and chipset and motherboard manufactures to promote an evolutionary new memory technology-DDR SDRAM. The group's role in accelerating market adoption of a DDR standard brings industry cooperation to a new level and provides leadership and direction, supporting component manufacturers while ensuring low cost, availability, and standardization. TeamDDR companies currently include ALi (Acer Labs), AMD, ATI, FCI, Hyndai, Infineon, InterWorks, Micron, NVIDIA, Samsung, SiliconTech, and VIA.

TSOP (Thin Small Outline Package) One of several packaging options for AMD flash devices.

uBGA (Micro Ball Grid Array) Next to bare die, uBGA is the smallest of the chip-scale packaging options.

Source: AMD (by022103)

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