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Glossary - Computer Video and Graphics

Glossary - Computer Video and Graphics

| What is SLI? | What is Crossfire? |

List of Video/Graphics Card manufacturers:
| ASUS | ATI/AMD | Connect3D | Diamond | EVGA | Galaxy | Gigabyte | Hauppauge | MSI | PNY | Powercolor | Sapphire | Visiontek | XFX | ZOTAC |

  • PCI Express/PCI-E
  • HDMI
  • DVI

  • DisplayPort
    DisplayPort is a digital display interface developed by the Video Electronics Standards Association (VESA). The interface is primarily used to connect a video source to a display device such as a computer monitor, though it can also be used to carry audio, USB, and other forms of data.

    The VESA specification is royalty-free. VESA designed it to replace VGA, DVI, and FPD-Link. DisplayPort is backward compatible with VGA and DVI through the use of adapter dongles.

    DisplayPort connector
  • Type: Digital audio/video connector
  • General specifications:
    - Hot pluggable: Yes
    - External Yes
    - Audio signal: Optional; 1C8 channels, 16 or 24-bit linear PCM; 32 to 192 KHz sampling rate; maximum bitrate 36,864 kbit/s (4.608 MB/s)
    - Video signal: Optional, maximum resolution limited by available bandwidth
    - Cable: 3 meters for full bandwidth transmission over passive cable. 33 meters over active cable.
    - Pins 20 pins for external connectors on desktops, notebooks, graphics cards, monitors, etc. and 30/20 pins for internal connections between graphics engines and built-in flat panels.
  • Electrical:
    - Signal: +3.3 V
    - Max. voltage: 16.0 V
    - Max. current: 0.5 Amp
  • Data:
    - Data signal: Yes
    - Bitrate: 1.62, 2.7, or 5.4 Gbit/s data rate per lane; 1, 2, or 4 lanes; (effective total 5.184, 8.64, or 17.28 Gbit/s for 4-lane link); 1 Mbit/s or 720 Mbit/s for the auxiliary channel.
    - Protocol: Mini-packet

  • 1.0 to 1.1
    DisplayPort 1.0 allows a maximum of 8.64 Gbit/s data rate over a 2-meter cable.[10] DisplayPort 1.1 also allows devices to implement alternative link layers such as fiber optic, allowing a much longer reach between source and display without signal degradation,[ although alternative implementations are not standardized. It also includes HDCP in addition to DisplayPort Content Protection (DPCP).

    DisplayPort version 1.2 was approved on December 22, 2009. The most significant improvement of the new version is the doubling of the effective bandwidth to 17.28 Gbit/s in High Bit Rate 2 (HBR2) mode, which allows increased resolutions, higher refresh rates, and greater color depth. Other improvements include multiple independent video streams (daisy-chain connection with multiple monitors) called Multi-Stream Transport, facilities for stereoscopic 3D, increased AUX channel bandwidth (from 1 Mbit/s to 720 Mbit/s), more color spaces including xvYCC, scRGB and Adobe RGB 1998, and Global Time Code (GTC) for sub 1 s audio/video synchronisation. Also Apple Inc.'s Mini DisplayPort connector, which is much smaller and designed for laptop computers and other small devices, is compatible with the new standard.

    DisplayPort version 1.2a will have as an optional feature VESA's Adaptive Sync.[15] AMD has been working on their FreeSync, which makes use of DisplayPort's capabilities. AMD demonstrated FreeSync at CES 2014[16] and later proposed VESA to standardize variable refresh rate features to DisplayPort standard.

    DisplayPort version 1.3, which was expected to be finalized in Q2 2014, will increase overall transmission bandwidth to 32.4 Gbit/s with the new HBR3 mode featuring 8.1 Gbit/s per lane (up from 5.4 Gbit/s with HBR2 in version 1.2). This will allow 8K resolution video, at either 76804320 (16:9, 33.18 megapixels) or 81924320 (~17:9, 35.39 megapixels), two 4K streams, or 4K 3D over a single cable. It will also support VESA Display Stream Compression, which uses a visually lossless low-latency algorithm, to offer increased resolutions and color depths, and reduced power consumption.

  • Companion standards
    Mini DisplayPort
    Mini DisplayPort (mDP) is a standard announced by Apple in the fourth quarter of 2008. Shortly after announcing the Mini DisplayPort, Apple announced that it would license the connector technology with no fee. The following year, in early 2009, VESA announced that Mini DisplayPort would be included in the upcoming DisplayPort 1.2 specification. On 24 February 2011, Apple and Intel announced Thunderbolt, a successor to Mini DisplayPort which adds support for PCI Express data connections while maintaining backwards compatibility with Mini DisplayPort based peripherals.

    Micro DisplayPort
    Micro DisplayPort will target systems that need ultra-compact connectors, such as phones, tablets and ultra-portable notebook computers. This new standard will be physically smaller than the currently available mini DisplayPort connectors. The standard is expected to be released by Q2 2014.

    Direct Drive Monitor (DDM) 1.0 standard was approved in December 2008. It allows for controller-less monitors where the display panel is directly driven by the DisplayPort signal, although the available resolutions and color depth are limited to two-lane operation.

    Embedded DisplayPort (eDP) 1.0 standard was adopted in December 2008. It aims to define a standardized display panel interface for internal connections; e.g., graphics cards to notebook display panels. It has advanced power-saving features including seamless refresh rate switching. Version 1.1 was approved in October 2009 followed by version 1.1a in November 2009. Version 1.2 was approved in May 2010 and includes DisplayPort 1.2 data rates, 120 Hz sequential color monitors, and a new display panel control protocol that works through the AUX channel. Version 1.3 was published in February 2011; it includes a new Panel Self-Refresh (PSR) feature developed to save system power and further extend battery life in portable PC systems. PSR mode allows GPU to enter power saving state in between frame updates by including framebuffer memory in the display panel controller. Version 1.4 is expected before end of 2012; it reduces power consumption with partial-frame updates in PSR mode, regional backlight control, lower interface voltage, and additional link rates; the auxiliary channel supports multi-touch panel data to accommodate different form factors.

    Internal DisplayPort (iDP) 1.0 was approved in April 2010. The iDP standard defines an internal link between a digital TV system on a chip controller and the display panel's timing controller. It aims to replace currently used internal FPD-Link lanes with DisplayPort connection. iDP features unique physical interface and protocols, which are not directly compatible with DisplayPort and are not applicable to external connection, however they enable very high resolution and refresh rates while providing simplicity and extensibility. iDP features non-variable 2.7 GHz clock and is nominally rated at 3.24 Gbit/s data rate per lane, with up to sixteen lanes in a bank, resulting in six-fold decrease in wiring requirements over FPD-Link for a 1080p24 signal; other data rates are also possible. iDP was built with simplicity in mind and it doesn't have AUX channel, content protection, or multiple streams; however it does have frame sequential and line interleaved stereo 3D.

    Portable Digital Media Interface (PDMI) is an interconnection between docking stations/display devices and portable media players, which includes 2-lane DisplayPort v1.1a connection. It has been ratified in February 2010 as ANSI/CEA-2017-A.

    Wireless DisplayPort (wDP) enables DisplayPort 1.2 bandwidth and feature set for cable-free applications operating in 60 GHz radio band; it was announced on November 2010 by WiGig Alliance and VESA as a cooperative effort.


    SlimPort, a brand of Analogix products, complies with Mobility DisplayPort, also known as MyDP, which is an industry standard for a mobile audio/video Interface, providing connectivity from mobile devices to external displays and HDTVs. SlimPort implements the transmission of video up to 4K-UltraHD and up to eight channels of audio over the micro-USB connector to an external converter accessory or display device. SlimPort products support seamless connectivity to DisplayPort, HDMI and VGA displays. The MyDP standard was released in June 2012, and the first product to use SlimPort was Google's Nexus 4 smartphone.

    SlimPort is an proprietary alternative to Mobile High-Definition Link (MHL).

    DisplayID is designed to replace the E-EDID standard. DisplayID features variable-length structures which encompass all existing EDID extensions as well as new extensions for 3D displays and embedded displays.

    The latest version 1.3 (anounced on 23 September 2013) adds enhanced support for tiled display topologies; it allows better identification of multiple video streams, and reports bezel size and locations. As of December 2013, many current 4K displays use a tiled topology, but lack a standard way to report to the video source which tile is left and which is right. These early 4K displays, for manufacturing reasons, typically use two 19202160 panels laminated together and are currently generally treated as multiple-monitor setups. DisplayID 1.3 also allows 8K display discovery, and has applications in stereo 3D, where multiple video streams are used.

    DockPort, formerly known as Lightning Bolt, is an extension to DisplayPort to include USB 3.0 data as well as power for charging portable devices from attached external displays. Originally developed by AMD and Texas Instruments, it has been announced as a VESA specification in 2014.
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  • PCI Express/PCI-E
    PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has numerous improvements over the aforementioned bus standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance-scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting (AER)), and native hot-plug functionality. More recent revisions of the PCIe standard support hardware I/O virtualization.

    The PCI Express electrical interface is also used in a variety of other standards, most notably in ExpressCard which is a laptop expansion card interface, and in SATA Express which is a computer storage interface.

    Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the conventional PCI specifications. PCIe 3.0 is the latest standard for expansion cards that is in production and available on mainstream personal computers.

  • Form factors
    PCI Express (standard)
    A PCIe card fits into a slot of its physical size or larger (maximum x16), but may not fit into a smaller PCIe slot (e.g.,a x16 card in a x8 slot). Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical connection. The number of lanes actually connected to a slot may also be less than the number supported by the physical slot size.

    An example is a x16 slot that runs at x4. This slot will accept any x1, x2, x4, x8, or x16 card, but provides only x4 speed. Its specification may read: x16 (x4 mode); "xsize @ xspeed" notation (x16 @ x4) is also common. The advantage is that such slot can accommodate a larger range of PCIe cards without requiring motherboard hardware to support the full transfer rate.

    All sizes of x4 and x8 PCI Express cards are allowed a maximum power consumption of 25 W. All x1 cards are initially 10 W; full-height cards may configure themselves as 'high-power' to reach 25 W, while half-height x1 cards are fixed at 10 W. All sizes of x16 cards are initially 25 W; like x1 cards, half-height cards are limited to this number while full-height cards may increase their power after configuration. They can use up to 75 W (3.3 V x 3 A + 12 V x 5.5 A), though the specification demands that the higher-power configuration be used for graphics cards only, while cards of other purposes are to remain at 25 W.

    Optional connectors add 75 W (6-pin) or 150 W (8-pin) power for up to 300 W total (2x75 W + 1x150 W). Some cards are using two 8-pin connectors, but this has not been standardized yet, therefore such cards must not carry the official PCI Express logo. This configuration would allow 375 W total (1x75 W + 2x150 W) and will likely be standardized by PCI-SIG with the PCI Express 4.0 standard. The 8-pin PCI Express connector could be mistaken with the EPS12V connector, which is mainly used for powering SMP and multi-core systems.

    PCI Express Mini Card
    PCI Express Mini Card (also known as Mini PCI Express, Mini PCIe, Mini PCI-E, mPCIe, and PEM), based on PCI Express, is a replacement for the Mini PCI form factor. It is developed by the PCI-SIG. The host device supports both PCI Express and USB 2.0 connectivity, and each card may use either standard. Most laptop computers built after 2005 are based on PCI Express.

    Physical dimensions
    PCI Express Mini Cards are 30x50.95 mm. There is a 52-pin edge connector, consisting of two staggered rows on a 0.8 mm pitch. Each row has eight contacts, a gap equivalent to four contacts, then a further 18 contacts. A half-length card is also specified 30x26.8 mm. Cards have a thickness of 1.0 mm (excluding components).

    Electrical interface
    PCI Express Mini Card edge connectors provide multiple connections and buses:
  • PCIe x1
  • USB 2.0
  • SMBus
  • Wires to diagnostics LEDs for wireless network (i.e., Wi-Fi) status on computer's chassis
  • SIM card for GSM and WCDMA applications. (UIM signals on spec)
  • Future extension for another PCIe lane
  • 1.5 and 3.3 volt power

    Mini PCI Express & mSATA
    Despite sharing the mini-PCI Express form factor, an mSATA slot is not necessarily electrically compatible with Mini PCI Express. For this reason, only certain notebooks are compatible with mSATA drives. Most compatible systems are based on Intel's Sandy Bridge processor architecture, using the Huron River platform. But for a mSATA/mini-PCI-E connector, the only prerequisite is that there is a switch which makes it either a mSATA or a mini-PCI-E slot and can be implemented on any platform.

    Notebooks like Lenovo's T-Series, W-Series, and X-Series ThinkPads released in March-April 2011 have support for an mSATA SSD card in their WWAN card slot. The ThinkPad Edge E220s/E420s, and the Lenovo IdeaPad Y460/Y560 also support mSATA.

    Some notebooks (notably the Asus Eee PC, the Apple MacBook Air, and the Dell mini9 and mini10) use a variant of the PCI Express Mini Card as an SSD. This variant uses the reserved and several non-reserved pins to implement SATA and IDE interface passthrough, keeping only USB, ground lines, and sometimes the core PCIe 1x bus intact. This makes the 'miniPCIe' flash and solid state drives sold for netbooks largely incompatible with true PCI Express Mini implementations.

    Also, the typical Asus miniPCIe SSD is 71 mm long, causing the Dell 51 mm model to often be (incorrectly) referred to as half length. A true 51 mm Mini PCIe SSD was announced in 2009, with two stacked PCB layers, which allows for higher storage capacity. The announced design preserves the PCIe interface, making it compatible with the standard mini PCIe slot. No working product has yet been developed.

    Intel has numerous desktop boards with the PCIe x1 Mini-Card slot which typically do not support mSATA SSD. A list of desktop boards that natively support mSATA in the PCIe x1 Mini-Card slot (typically multiplexed with a SATA port) is provided on the Intel Support site.

    PCI Express External Cabling
    PCI Express External Cabling (also known as External PCI Express, Cabled PCI Express, or ePCIe) specifications were released by the PCI-SIG in February 2007.

    Standard cables and connectors have been defined for x1, x4, x8, and x16 link widths, with a transfer rate of 250 MB/s per lane. The PCI-SIG also expects the norm will evolve to reach 500 MB/s, as in PCI Express 2.0. The maximum cable length remains undetermined. An example of the uses of Cabled PCI Express is a metal enclosure, containing a number of PCI slots and PCI-to-ePCIe adapter circuitry. This device would not be possible had it not been for the ePCIe spec.

  • History and revisions
    PCI Express 1.0a
    In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250 MB/s and a transfer rate of 2.5 gigatransfers per second (GT/s). Transfer rate is expressed in transfers per second instead of bits per second because the number of transfers includes the overhead bits, which do not provide additional throughput.

    PCIe 1.x uses an 8b/10b encoding scheme that results in a 20 percent ((10−8)/10) overhead on the raw bit rate. It uses a 2.5 GHz clock rate, therefore delivering an effective 250 000 000 bytes per second (250 MB/s) maximum data rate.

    PCI Express 1.1
    In 2005, PCI-SIG introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate.

    PCI Express 2.0
    PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s. This means a 32-lane PCIe connector (x32) can support throughput up to 16 GB/s aggregate.

    PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 will work with the other being v1.1 or v1.0a.

    The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.

    Intel's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007. AMD started supporting PCIe 2.0 with its AMD 700 chipset series and nVidia started with the MCP72. All of Intel's prior chipsets, including the Intel P35 chipset, supported PCIe 1.1 or 1.0a.

    Like 1.x, PCIe 2.0 uses an 8b/10b encoding scheme, therefore delivering, per-lane, an effective 4 Gbit/s max transfer rate from its 5 GT/s raw data rate.

    PCI Express 2.1
    PCI Express 2.1 supports a large proportion of the management, support, and troubleshooting systems planned for full implementation in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. Unfortunately, the increase in power from the slot breaks backward compatibility between PCI Express 2.1 cards and some older motherboards with 1.0/1.0a, but most motherboards with PCI Express 1.1 connectors are provided with a BIOS update by their manufacturers through utilities to support backward compatibility of cards with PCIe 2.1.

    PCI Express 3.x
    PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until 2011. New features for the PCI Express 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.

    Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCI Express protocol stack.

    PCI Express 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the overhead to approximately 1.54% ((130-128)/130), as opposed to the 20% overhead of PCI Express 2.0. This is achieved by a technique called "scrambling" that applies a known binary polynomial to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial. PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, practically doubling the lane bandwidth relative to PCI Express 2.0.

    On November 18, 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.

    PCI Express 3.1 specification is scheduled to be released in late 2013 or early 2014, consolidating various improvements to the published PCI Express 3.1 specification in three areas - power management, performance and functionality.

    PCI Express 4.0
    On November 29, 2011, PCI-SIG announced PCI Express 4.0 featuring 16 GT/s, still based on copper technology. Additionally, active and idle power optimizations are to be investigated. Final specifications are expected to be released in 2014 or 2015.

    | AMD/ATI Video Cards | nVIDIA GeForce Graphics | PCI Express Video Cards | Video Card Driver Updates & Downloads |

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    2D Graphics / 3D Graphics /3D Pipeline / Alpha Blending / Alpha Buffer / Anti-aliasing / Atmospheric Effect / Bitmap / Bilinear Filtering / BitBLTs / Blending / Bus Mastering / Chroma Keying / Depth Cueing / Dithering / Double Buffering / DRAM / EDO DRAM / Flat Shading / Fog / Gamma / Gamma Correction / Gouraud Shading / Hidden Surface Removal / Interpolation / Lightning / Line Buffer / MIP Mapping / Occlusion / Palletized Texture / Perspective Correction / Phong Shading / Projection / Resterization / Rendering / Rendering Engine / Scissors Clip / Set-up Engine / SDRAM / SGRAM / Span / Tessellation / Texture Anti-Aliasing / Texture Filtering / Texture Mapping / Transformation / Tri-Linear Filtering / Tri-Linear MIP Mapping / Z-buffer / Z-buffering / Z-Sorting


    2D Graphics
    Displayed representation of a scene or an object along two axes of reference: height and width (x and y).

    3D Graphics
    Displayed representation of a scene or an object that appears to have three axes of reference: height, width, and depth  (x, y, and z).

    3D Pipeline
    The process of 3D graphics can be divided into three-stages: tessellation, geometry, and rendering. In the tessellation stage, a described model of an object is created, and the object is then converted to a set of polygons. The geometry stage includes transformation, lighting, and setup. The rendering stage, which is critical for 3D image quality, creates a two dimensional display from the polygons created in the geometry stage.

    Alpha Blending
    The real world is composed of transparent, translucent, and opaque objects. Alpha blending is a technique for adding transparency information for translucent objects. It is implemented by rendering polygons through a stipple mask whose on-off density is proportional to the transparency of the object. The resultant color of a pixel is a combination of the foreground and background color.
    Typically, alpha has a normalized value of 0 to 1 for each color pixel.
    new pixel = (alpha)(pixel A color) + (1 - alpha)(pixel B color)

    Alpha Buffer
    An extra Color channel to hold transparency information; pixels become quad values (RGBA). In a 32-bit frame buffer there are 24 bits of color, 8 each for red, green, and blue, along with an 8-bit alpha channel.

    Anti-aliasing is sub pixel interpolation, a technique that makes edges appear to have better resolution.

    Atmospheric Effect
    Effects, such as fog and depth cueing, that improve the rendering of real-world environments.

    A Bitmap is a pixel by pixel image.

    Bilinear Filtering
    Bilinear filtering is a method of anti-aliasing texture maps. A texture-aliening artifact occurs due to sampling on a finite pixel grid. Point-sampled telexes jump from one pixel to another at random times. This aliening is very noticeable on slowly rotating or moving polygons. The texture image jumps and shears along pixel boundaries. To eliminate this problem, bilinear filtering takes a weighted average of four adjacent texture pixels to create a single telex.

    The BitBLT is the single most important acceleration function for windowed GUI environments. A BitBLT is simply the movement of a block of data from one place to another, taking into account the special requirements and arrangements of the graphics memory. For example, this function is utilized every time a window is moved; in which case, the BitBLT is a simple Pixel Block Transfer. More complicated cases may occur where some transformation of the source data is to occur, such as in a Color Expanded Block Transfer, where each monochromatic bit in the source is expanded to the color in the foreground or background register before being written to the display.

    Blending is the combining of two or more objects by adding them on a pixel-by-pixel basis.

    Bus Mastering
    A feature of PCI buses that allows a card with this feature to retrieve data directly from system memory without any interaction with the host CPU

    Chroma Keying
    Chroma Keying or texture transparency is the ability to recognize a key color within a texture map and make it transparent during the texture mapping process. Since not all objects are easily modeled with polygons, chroma keying is used to include complex objects in a scene as texture maps.

    Depth Cueing
    Depth cueing is the lowering of intensity as objects move away from the viewpoint.

    Dithering is a technique for archiving 24-bit quality in 8 or 16-bit frame buffers. Dithering uses two colors to create the appearance of a third, giving a smooth appearance to an otherwise abrupt transition.

    Double Buffering
    A method of using two buffers, one for display and the other for rendering. While one of the buffers is being displayed, the other buffer is operated on by a rendering engine. When the new frame is rendered, the two buffers are switched. The viewer sees a perfect image all the time.

    Dynamic Random Access Memory is the memory at any location in a computer that can be accessed immediately for reading and writing operations.

    A type of DRAM that has enhanced readability in the Extended-Data-Out mode.

    Flat Shading
    The flat shading method is also called constant shading. For rendering, it assigns a uniform color throughout an entire polygon. This shading results in the lowest quality, an object surface with a faceted appearance and a visible underlying geometry that looks 'blocky'.

    Fog is the blending of an object with a fixed color as its pixels become farther away from the viewpoint.

    The characteristics of displays using phosphors (as well as some cameras) are nonlinear. A small change in voltage when the voltage level is low produces a change in the output display brightness level; but this same small change in voltage at a high voltage level will not produce the same magnitude of change in the brightness output. This effect, or actually the difference between what you should have and what you actually measured, is known as gamma.

    Gamma Correction
    Before being displayed, linear RGB data must be processed (gamma corrected) to compensate for the gamma (nonlinear characteristics) of the display.

    Gouraud Shading
    Gouraud shading, one of the most popular smooth shading algorithms, is named after its French originator, Henri Gouraud. Gouraud shading, or color interpolation, is a process by which color information is interpolated across the face of the polygon to determine the colors at each pixel. It assigns color to every pixel within each polygon based on linear interpolation from the polygon's vertices. This method improves the 'blocky' (see Flat Shading) look and provides an appearance of plastic or metallic surfaces.

    Hidden Surface Removal
    Hidden Surface Removal or visible surface determination entails displaying only those surfaces that are visible to a viewer because objects are a collection of surfaces or solids.

    Interpolation is a mathematical way of regenerating missing or needed information. For example, an image needs to be scaled up by a factor of two, from 100 pixels to 200 pixels. The missing pixels are generated by interpolating between the two pixels that are on either side of the pixel that needs to be generated. After all of the 'missing' pixels have been interpolated, 200 pixels exist where only 100 existed before, and the image is twice as big as it used to be.

    There are many techniques for creating realistic graphical effects to simulate a real-life 3-D object on a 2-D display. One technique is lighting. Lighting creates a real-world environment by means of rendering the different grades of darkness and brightness of an object's appearance to make the object look solid.

    Line Buffer
    A line buffer is a memory buffer used to hold one line of video. If the horizontal resolution of the screen is 640 pixels and RGB is used as the color space, the line buffer would have to be 640 locations long by 3 bytes wide. This amounts to one location for each pixel and each color plane. Line buffers are typically used in filtering algorithms.

    MIP Mapping
    Multum in Parvum (Latin) means 'many in one'. A method of increasing the quality of a texture map by applying different-resolution texture maps for different objects in the same image, depending on their size and depth. If a texture-mapped polygon is smaller than the texture image itself, the texture map will be undersampled during rasterization. As a result, the texture mapping will be noisy and 'sparkly'. The purpose of MIP mapping is to remove this effect.

    The effect of one object in 3-D space blocking another object from view.

    Palletized Texture
    Palletized Texture means compressed texture formats, such as 1-, 2-, 4-, and 8-bit instead of 24-bit; this allows more textures to be stored in less memory.

    Perspective Correction
    A particular way to do texture mapping; it is extremely important for creating a realistic image. It takes into account the effect of the Z value in a scene while mapping texels onto the surface of polygons. As a 3D object moves away from the viewer, the length and height of the object become compressed, making it appear shorter. Without perspective correction, objects will appear to shift and 'tear' in an unrealistic way. True perspective correction is that the rate of change per pixel of texture is proportional to the depth. Since it requires a division per pixel, perspective correction is very computing intensive.

    Phong Shading
    Phong shading is a sophisticated smooth shading method, originated by Phong Bui-tuong. The Phong shading algorithm is best known for its ability to render precise, realistic specula highlights. During rendering, Phong shading achieves excellent realism by calculating the amount of light on the object at tiny points across the entire surface instead of at the vertices of the polygons. Each pixel representing the image is given its own color based on the lighting model applied at that point. Phong shading requires much more computation for the hardware than Gouraud shading.

    The process of reducing three dimensions to two dimensions for display is called Projection. It is the mapping of the visible part of a three dimensional object onto a two dimension screen.

    Translating an image into pixels.

    The process of creating life-like images on a screen using mathematical models and formulas to add shading, color, and lamination to a 2D or 3D wireframe.

    Rendering Engine
    "Rendering Engine" generically applies to the part of the graphics engine that draws 3D primitives, usually triangles or other simple polygons. In most implementations, the rendering engine is responsible for interpolation of edges and "filling in" the triangle.

    Scissors Clip
    Test pixel coordinates against clip rectangles and reject them if outside.

    Set-up Engine
    A set-up engine allows drivers to pass polygons to the rendering engine in the form of raw vertex information, subpixel polygon addresses. Whereas, most common designs force the host CPU to pre-process polygons for the rendering engine in terms of delta values for edges, color, and texture. Thus, a set-up engine moves processing from the host CPU to the graphics chip, reducing bus bandwidth requirements by 30% for small, randomly placed triangles and by proportionately more for larger polygons.

    Synchronous DRAM is a type of DRAM to which reads or writes can be performed synchronously with the memory clock and at much higher speeds than with Fast-Page or EDO DRAM.

    Synchronous Graphics Random Access memory (SGRAM) is a type of memory that is optimized for graphics use. SGRAM is capable of running at much higher speeds than fast page or EDO DRAM. SGRAM is able to execute a small number of frequently executed operations, such as buffer clears, specific to graphics applications independently of the controller.

    In raster graphics architecture a primitive is formed by scan conversion where each scan line intersects the primitive at two ends, P left and P right. A contiguous sequence of pixels on the scan line between P left and P right is called a Span. Each pixel within the span contains the z, R, G, and B data values.

    Processing 3D graphics can be pipelined into three-stages: tessellation, geometry, and rendering. Tessellation is the process of subdividing a surface into smaller shapes. To describe object surface patterns, tessellation breaks down the surface of an object into manageable polygons. Triangles or quadrilaterals are two usually used polygons in drawing graphical objects because computer hardware can easy manipulate and calculate these two simple polygons.

    An object divided into quads and subdivided into triangles for convenient calculation.

    Texture Anti-aliasing
    An interpolation technique used to remove texture distortion, staircasing or jagged edges, at the edges of an object.

    Texture Filtering
    Removing the undesirable distortion of a raster image, also called aliasing artifacts, such as sparkles and blockiness, through interpolation of stored texture images.

    Texture Mapping
    Texture mapping is based on a stored bitmap consisting of texture pixels, or texels. It consists of wrapping a texture image onto an object to create a realistic representation of the object in 3D space. The object is represented by a set of polygons, usually triangles. The advantage is complexity reduction and rendering speed, because only one texel read is required for each pixel being written to the frame buffer. The disadvantage is the blocky image that results when the object moves.

    Change of coordinates; a series of mathematical operations that act on output primitives and geometric attributes to convert them from modeling coordinates to device coordinates.

    Tri-linear Filtering
    Based on bilinear filtering, trilinear filtering takes the weighted average of two levels of bilinear filtering results to create a single telex. The resultant graphics image is smoother and less flashy.

    Tri-linear MIP Mapping
    A method of reducing aliasing artifacts within texture maps by applying a bilinear filter to four texels from the two nearest MIP maps and then interpolating between the two.

    A part of off-screen memory that holds the distance from the viewpoint for each pixel, the Z-value. When objects are rendered into a 2D frame buffer, the rendering engine must remove hidden surfaces.

    A process of removing hidden surfaces using the depth value stored in the Z-buffer. Before bringing in a new frame, the rendering engine clears the buffer, setting all Z-values to 'infinity'. When rendering objects, the engine assigns a Z-value to each pixel: the closer the pixel to the viewer, the smaller the Z value. When a new pixel is rendered, its depth is compared with the stored depth in the Z-buffer. The new pixel is written into the frame buffer only if its depth value is less than the stored one.

    A process of removing hidden surfaces by sorting polygons in back-to-front order prior to rendering. Thus, when the polygons are rendered, the forward-most surfaces are rendered last. The rendering results are correct unless objects are close to or intersect each other. The advantage is not requiring memory for storing depth values. The disadvantage is the cost in more CPU cycles and limitations when objects penetrate each other.


    (Source: Trident)

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